1. Field of the Invention:
The invention relates to the generation of a digital clock signal. More specifically, this invention relates to the generation of a clock signal based upon a system clock signal, where the duty cycle of the generated clock signal may be tuned and is independent of the system clock signal.
2. Art Background:
Many digital systems, including most computers, employ a system clock to synchronize various system operations. Typically, digital systems generate the system clock signal with an oscillator circuit implemented with a crystal. The system clock signal is generally a square wave pulse train where the amplitude of the wave corresponds to the voltage difference between the high and low states of the digital system. The clock signal is an input into various circuits that perform operations during that part of the clock period where the clock signal is at its maximum value, the voltage that corresponds to the high state of the system. The duty cycle of a clock is defined as the ratio of the pulse width which corresponds to the amount of time during which the signal is at a maximum value, to the total period of the clock.
Certain system operations, which may be called sub-systems, may require a different duty cycle than that provided by the system clock. Reads and writes to memory are examples of system operations that may require a longer duty cycle than other operations. For system synchronization, however, it is still desirable to perform all of the system operations, including those operations that require a longer or shorter duty cycle, based upon the system clock. That is, each system operation should be performed within the same period of the clock.
It is not efficient to employ different oscillator circuits for each sub-system that requires a different duty cycle than that provided by the system clock. First, as previously stated, the system must be synchronized. Although certain operations may require a longer or shorter duty cycle, the system should synchronize the start of these various operations such that after one clock cycle, each system has performed its operation. The use of different oscillator circuits would tend to desynchronize the system since the periods of the various oscillators may diverge over time. Further, the use of additional oscillators would increase the cost of the system.
The present invention overcomes the limitations of prior art systems by providing a method and apparatus that generates clock signals with the same period as a system clock but with a longer or shorter duty cycle than that provided by the system clock. Further, as will be described more fully below, the method and apparatus of the present invention allows the duty cycle of the system to be accurately extended or shortened to any desired value.